This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2003-121631, filed Apr. 25, 2003, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a system using the semiconductor integrated circuit device and, more particularly, is applied to a high-speed input/output circuit which transmits a pair of differential signals.
2. Description of the Related Art
Recently, the speed of an input/output circuit (to be simply referred to as an I/O circuit) increases, and a semiconductor integrated circuit device must process an input/output signal in the GHz band. To process a signal of such high frequency by the I/O circuit, for example, a pair of differential signals resistant to noise are used for the input and output. Alternatively, bump connection capable of implementing a short, uniform wiring length is used for connection between an LSI and a package.
FIG. 1 shows an output circuit (differential output driver circuit) which transmits a pair of differential signals, in order to explain a conventional semiconductor integrated circuit device. A differential output driver circuit 11 comprises differential input MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) 12 and 13, load elements 14 and 15, and a constant-current source 16. The gates of the differential input MOSFETs 12 and 13 receive a pair of differential signals from a circuit 17 on the input stage. The load elements 14 and 15 are respectively connected between the drains of the differential input MOSFETs 12 and 13 and a power supply VDD. The sources of the differential input MOSFETs 12 and 13 are commonly connected, and the constant-current source 16 is connected between the common source node and ground VSS.
One end of a global interconnection 18 is connected to the node between the drain of the MOSFET 13 and the load element 15, and the other end is connected to a bump 20. One end of a global interconnection 19 is connected to the node between the drain of the MOSFET 12 and the load element 14, and the other end is connected to a bump 21. The bumps 20 and 21 function as IC or LSI output terminals and are formed on a chip surface. Each of the bumps 20 and 21 is connected to one end of a corresponding one of transmission lines 22 and 23 formed within a package (bonding wires, lead frame, TAB tape, or the like) or on a printed circuit board on which the semiconductor integrated circuit device is mounted.
In a system LSI, many differential output driver circuits 11 are arranged at I/O portions. The transmission lines 22 and 23 are terminated by the same resistances as the characteristic impedances of the transmission lines 22 and 23 on the receiving side, which is not shown in FIG. 1.
If the differential output driver circuit 11 operates ideally, the circuit 11 is resistant to external noise. However, the following problems occur because of the presence of many I/O circuits within the chip.
(a) If the signal line lengths of a pair of differential signals are not equal to each other, a skew in propagation delay time occurs at the ends of the transmission lines 22 and 23.
(b) The skew generates an in-phase current between the transmission lines 22 and 23 (ideally no in-phase current is generated), generating noise (common mode noise) which is radiated upon coupling with a neighboring pattern.
Examples of the line length difference which causes problems (a) and (b) are as follows.
(1) The wiring length difference between the transmission lines 22 and 23 formed within a package (bonding wire, lead frame, or TAB tape) or on a printed circuit board.
(2) The wiring length difference between the global interconnections 18 and 19 which respectively connect the load elements 14 and 15 and the bumps 20 and 21.
As for difference (1), the wiring lengths are often adjusted by bending one wire into a U shape on the printed circuit board so as to make the wiring lengths equal to each other. If the frequency of a pair of differential signals increases to the GHz band, the U-shaped wire undesirably radiates electromagnetic waves. As the number of I/O portions increases, many U-shaped wires must be arranged on the printed circuit board, increasing the transmission line layout area.
As for difference (2), the wiring lengths are adjusted on the LSI similarly to difference (1). Adjustment of the lengths of a pair of differential lines on the LSI for all I/O portions wastes the space. The return current from ground suffers a path difference depending on the positional relationship between a bump serving as a ground terminal and the signal input/output bumps 20 and 21. A skew equal to or larger than the line length difference between the global interconnections 18 and 19 may occur. At a GHz-band frequency, the wiring length difference between the global interconnections 18 and 19 may generate a skew or common mode noise.
As described above, to reduce a skew or common mode noise, the line lengths of a pair of the differential lines must be kept as equal to each other as possible. In practice, the line length difference between a pair of differential lines cannot be eliminated owing to variations caused by the manufacturing tolerance of the package or printed circuit board.
Especially when a pair of differential signals have a GHz-band frequency, such variations greatly influence the transmission characteristic. In mass production, a system having a function of checking a margin for manufacturing variations is required.
For example, Japanese Patent No. 3,144,199 discloses a skew correction circuit using a differential amplifier and resistor. If the skew correction circuit is arranged at each I/O portion, the area occupied on the chip greatly increases due to a large circuit scale. Application of the skew correction circuit to a semiconductor integrated circuit device which processes a signal of a high GHz-band frequency is not practical.
In this manner, the conventional semiconductor integrated circuit device generates a skew or common mode noise by the line length difference between a pair of differential lines.
In mass production, a system using a semiconductor integrated circuit device capable of checking a margin for manufacturing variations is required.
According to one aspect of the present invention, there is provided a semiconductor integrated circuit device comprising a chip on which an integrated circuit is formed, a differential output driver circuit which externally outputs a pair of differential signals generated by the integrated circuit, first and second signal lines which transmit the pair of differential signals output from the differential output driver circuit, and a delay unit which is connected in the chip to at least one of the first and second signal lines, has an active element for delaying signals passing through the first and second signal lines so as to make delays of the signals substantially equal to each other, and compensates for a signal delay time generated by a line length difference between the first and second signal lines.
According to another aspect of the present invention, there is provided a semiconductor integrated circuit device comprising a chip on which an integrated circuit is formed, a differential output driver circuit which externally outputs a pair of differential signals generated by the integrated circuit, first and second signal lines which transmit the pair of differential signals output from the differential output driver circuit, and a delay unit which is connected in the chip to at least one of third and fourth signal lines which transmit the pair of differential signals from the integrated circuit to the differential output driver circuit, has an active element for delaying at least one of the pair of differential signals so as to make delays of the signals passing through the first and second signal lines substantially equal to each other, and compensates for a signal delay time generated by a line length difference between the first and second signal lines.
According to still another aspect of the present invention, there is provided a system using a semiconductor integrated circuit device, comprising a semiconductor integrated circuit device comprising a differential output driver circuit which externally outputs via first and second signal lines a pair of differential signals generated within a chip, a first receiving unit which receives the pair of differential signals output from the semiconductor integrated circuit device via the first and second signal lines, a signal processing unit which processes the pair of differential signals received by the first receiving unit and generates correction data for correcting unbalance between the pair of differential signals, a transmitting unit which transmits the correction data generated by the signal processing unit to the semiconductor integrated circuit device, a second receiving unit which is arranged in the semiconductor integrated circuit device and receives the correction data transmitted from the transmitting unit, and a delay unit which changes a delay time on the basis of the correction data received by the second receiving unit, has an active element for delaying signals passing through the first and second signal lines so as to make delays of the signals substantially equal to each other, and compensates for a signal delay time generated by a line length difference between the first and second signal lines.